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The applications of silicon compilers, and the design methodology of the Genesil Silicon Compiler are described. The performance of Genesil system library adders and multipliers are compared with comparable custom pipelined adder and multiplier circuits built on the Genesil Silicon Compiler. High performance pipeline methods are discussed. The appendix is a tutorial illustrating a Genesil system hierarchical top-down chip design, including simulation and timing analysis procedures. Keywords: Genesil silicon compiler design methodology; Custom 16 bit pipelined adder and multiplier performance; Top-down chip-design. Theses.