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Katzenelson's algorithm and its variants are powerful tools for solving nonlilnear networks which are modeled by piecewise-linear characteristics. But, when nonlinear network sizes become very large such as in VLSI chip cases, excessive cpu time and storage are required during the solution process using Katzenelson's algorithms. Decomposition techniques are necessary in the analysis of VLSI circuits. Nonlinear Gauss-Seidel iterative methods are often adopted in solving large decomposed system of equations. However, Nonlinear Gauss-Seidel iterative process will converge under certain conditions. The combination of Katzenelson and Gauss-Seidel methods proposed here takes advantages of both Katzenelson and the Gauss-Seidel methods. It decomposes the whole network into small subcircuits by Gauss-Seidel method and solves these small subcircuits by Katzenelson's algorithm separately (or even these subcircuits can be solved by Katzenelson's at same time with parallel processors, if Jacobi Method is used as decompositions technique). The convergence properties of the method is studies in detail, and examples are given here to illustrate the approach in the dc analysis of bipolar and MOS transistors circuits: Keywords: Nonlinear integrated circuits; Convergence; Computer programs; Schematic diagrams.