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In order to appreciate the critical hardware and software problems associated with the definition and design of very large scale integrated circuits or integrated systems including 10,000 - 1,000,000 transistors in a single silicon chip, incisive experiments conducted with actual operating chips are indispensible. The objective of this project is to establish, within a university research environment, a facility for the rapid execution of mask generation, wafer fabrication, and functional testing of user-generated custom I.C. designs.