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There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

There is a growing trend toward using high-level tools for design and implementation of radio astronomy digital signal processing (DSP) systems. Such tools, for example, those from the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER), are usually platform-specific, and lack high-level, platform-independent, portable, scalable application specifications. This limits the designer's ability to experiment with designs at a high-level of abstraction and early in the development cycle. We address some of these issues using a model-based design approach employing dataflow models. We demonstrate this approach by applying it to the design of a tunable digital downconverter (TDD) used for narrow-bandwidth spectroscopy. Our design is targeted toward an FPGA platform, called the Interconnect Break-out Board (IBOB), that is available from the CASPER. We use the term TDD to refer to a digital downconverter for which the decmation factor and center frequency can be reconfigured without the need for regenerating the hardware code. Such a design is currently not available in the CASPER DSP library. The work presented in this paper focuses on two aspects. Firstly, we introduce and demonstrate a dataflow-based design approach using the dataflow interchange format (DIF) tool for high-level application specification, and we integrate this approach with the CASPER tool flow. Secondly, we explore the trade-off between the flexibility of TDD designs and the low hardware cost of fixed-configuration digital downconverter (FDD) designs that use the available CASPER DSP library. We further explore this trade-off in the context of a two-stage downconversion scheme employing a combination of TDD or FDD designs.

AD775038

Trimester 1 2016/2017

The first series of results of a major research project for the analysis of the electroencephalogram (EEG) are reported. The requirements of a system capable of real time, multidimensional analysis of the EEG are described. The time and frequency domain computer analysis programs written for the project are discussed. A major result of the research indicates that a significant portion of the EEG is composed of a series of discrete frequency sinusoids. These signals have a spindle shape and their average durations are constant over the frequency range from 14 to 50 Hz, with the exception of sinusoids of 42 Hz. The signals are defined as tegules. The properties of a tegule are defined, as found from experimental results. The anomaly with respect to the 42 Hz tegule is related to the subject's mental state and may be a source of feedback to indicate whether he is thinking or relaxing.

The first series of results of a major research project for the analysis of the electroencephalogram (EEG) are reported. The requirements of a system capable of real time, multidimensional analysis of the EEG are described. The time and frequency domain computer analysis programs written for the project are discussed. A major result of the research indicates that a significant portion of the EEG is composed of a series of discrete frequency sinusoids. These signals have a spindle shape and their average durations are constant over the frequency range from 14 to 50 Hz, with the exception of sinusoids of 42 Hz. The signals are defined as tegules. The properties of a tegule are defined, as found from experimental results. The anomaly with respect to the 42 Hz tegule is related to the subject's mental state and may be a source of feedback to indicate whether he is thinking or relaxing.

We present a new, patent pending, modulation technique called smoothed symbol transition modulation (SSTM). Smoothed symbol transition modulation removes the rectangular windowing function limitations present in conventional modulation techniques. Conventional modulation is limited by the instantaneous step changes between symbols. In binary frequency shift keying (FSK), for the message {0, 1,}, there is a step change in transitioning from 0 to 1. In quadrature amplitude modulation (QAM), each in-phase, I, and quadrature phase, Q, symbol is transmitted for 1 symbol time. For the symbol transition, I(n-1) to I(n), assuming I(n-1) .. I(n), there is also a step change. The same step changes also occur in the quadrature channel. The embedded rectangular windowing functions present in conventional modulation are from the instantaneous step changes. The step changes always occur at multiples of the symbol time. Conventional modulation is also limited by the modulator'.'s dynamic behavior during a symbol transition. Smoothed symbol transition modulation replaces the step changes with smooth, zero slope transitions between symbols. For smoothed symbol transition modulation, a symbol transition occurs over 1 symbol time; not an instantaneous step change. Smoothed symbol transition modulation uses half cycle raised cosine waveforms, and zero slope line segments to create a smooth waveform with zero slope symbol transition points. The smooth waveform and zero slope symbol transition points reduce channel bandwidth. SSTM offers opportunities for improved performance under intersymbol interference, multipath signal conditions, dispersive channel conditions (arctic flutter), and timing jitter conditions. We present simulations comparing conventional FSK and QAM to smoothed symbol transition modulation FSK and QAM respectively. We show considerable improvements in bandwidth and power spectral density. SSTM is a general concept that can be incorporated in any digital modulation system. Potential applications for SSTM include narrow band systems, multi-channel DSL modems, crowded frequency channels, and urban multipath environments.

Click here to view the University of Florida catalog record

Click here to view the University of Florida catalog record

Click here to view the University of Florida catalog record

Combine all lecture notes and problem solution become 1 PDF gilr from class MIT RES 6.008 Spring 2011 - Digital Signal Processing.

Trimester 3 2022/2023

Tri 2 2022/2023

Trimester 3 - 2016/2017

Trimester 2 2018/2019

Trimester 2 2018/2019

An acquisition system of digital nuclear signal processing for the algorithm development 作者： WANG Peng 1 ZHANG Ruanyu 2 YAN Yangyang 2 HAO Dejian 2 HUANG Ning 1 WU Qingxing 1 AN Zhu 1 作者单位： 1. Institute of Nuclear Science and Technology of Sichuan University, Key Laboratory of Radiation Physics and Technology, Ministry of Education, Chengdu 610064,China 2. The College of Physics Science and Technology of Sichuan University,Chengdu 610064,China 提交时间： 2023-06-18 摘要: A principle and method of constructing the digital acquisition system is presented in this work, which is convenient for the study on the theories and algorithms of digital nuclear signal processing. The hardware system of the digital acquisition system consists of front-end controller, waveform digitizer and PC workstation, on which the software system has been developed based on Visual C++ under Windows environment. The alterable-frequency sampling (AFS) algorithm and the alterable-frequency trapezoidal filter (AFTF) algorithm have also been studied in the real-time environment, along with a digital nuclear spectrum acquisition system being set up based on the new algorithms and the -ray spectra of 241Am being shown. A useful experimental platform could be provided by this work for the successive work such as the development of global digitized nuclear measurement system and the study of digital nuclear signal processing. Digitized nuclear instrument Digital nuclear signal processing Digitized nuclear measurement 期刊： Nuclear Science and Techniques 分类： 核科学技术 >> 核探测技术与核电子学 投稿状态： 已在期刊出版 引用： ChinaXiv:202306.00548 (或此版本 ChinaXiv:202306.00548V1 ) DOI:dx.doi.org/10.13538/j.1001-8042/nst.2013.06.012 CSTR:32003.36.ChinaXiv.202306.00548.V1 推荐引用方式： WANG Peng,ZHANG Ruanyu,YAN Yangyang,HAO Dejian,HUANG Ning,WU Qingxing,AN Zhu.(2023).An acquisition system of digital nuclear signal processing for the algorithm development.Nuclear Science and Techniques.doi:dx.doi.org/10.13538/j.1001-8042/nst.2013.06.012 版本历史 [V1] 2023-06-18 16:55:08 ChinaXiv:202306.00548V1 下载全文

Research supported by this grant has been concentrated in four distinct, but related projects: (1) an analysis of inherent phase distortion in rectangular and polar format FFT processing algorithms, (2) a SAR computer simulation with polar format recording, (3) a study of 2D interpolators for polar-to-rectangular coordinate transformation, and (4) an investigation of number theoretic concepts for high speed failure resistant digital processors required in real-time SAR systems. (Author)

Research supported by this grant has been concentrated in four distinct, but related projects: (1) an analysis of inherent phase distortion in rectangular and polar format FFT processing algorithms, (2) a SAR computer simulation with polar format recording, (3) a study of 2D interpolators for polar-to-rectangular coordinate transformation, and (4) an investigation of number theoretic concepts for high speed failure resistant digital processors required in real-time SAR systems. (Author)

From the bitsavers.org collection, a scanned-in computer-related document. ti :: TMS320xx :: Digital Signal Processing Applications with the TMS320 Family Vol 3 1990

Scan of book Programs for digital signal processing by Digitial Signal Processing Committee of the IEEE [1979] {621.38'043--loc} Fortran programs on state of the art computers of the time Note: a set of corrections was published the following year

The current digital signal analysis algorithms are investigated that are implemented in automatic voice recognition algorithms. Automatic voice recognition means, the capability of a computer to recognize and interact with verbal commands. The digital signal is focused on, rather than the linguistic, analysis of speech signal. Several digital signal processing algorithms are available for voice recognition. Some of these algorithms are: Linear Predictive Coding (LPC), Short-time Fourier Analysis, and Cepstrum Analysis. Among these algorithms, the LPC is the most widely used. This algorithm has short execution time and do not require large memory storage. However, it has several limitations due to the assumptions used to develop it. The other 2 algorithms are frequency domain algorithms with not many assumptions, but they are not widely implemented or investigated. However, with the recent advances in the digital technology, namely signal processors, these 2 frequency domain algorithms may be investigated in order to implement them in voice recognition. This research is concerned with real time, microprocessor based recognition algorithms.

Project report.

Project report.

Project report.

Lectures from the course webcast. Copied to archive.org on closure of the UCBerkeley webcast site in order to preserve access. Note: some lectures may appear to be missing (gap in numbering). This usually means that there was a holiday, exam, or no lecture on the day the recording was due, although sometimes it does mean that the recording is not available.

Lectures from the course webcast. Copied to archive.org on closure of the UCBerkeley webcast site in order to preserve access. Note: some lectures may appear to be missing (gap in numbering). This usually means that there was a holiday, exam, or no lecture on the day the recording was due, although sometimes it does mean that the recording is not available.

Research directions in the fields of digital signal processing and modern control and estimation theory are discussed. Stability theory, linear prediction and parameter identification, system synthesis and implementation, two-dimensional filtering, decentralized control and estimation, and image processing are considered in order to uncover some of the basic similarities and differences in the goals, techniques, and philosophy of the disciplines.

Research directions in the fields of digital signal processing and modern control and estimation theory are discussed. Stability theory, linear prediction and parameter identification, system synthesis and implementation, two-dimensional filtering, decentralized control and estimation, and image processing are considered in order to uncover some of the basic similarities and differences in the goals, techniques, and philosophy of the disciplines.

Topics covered involve a number of closely related tasks including: the development of several control loop and dynamic noise model computer programs for simulating microwave radiometer measurements; computer modeling of an existing stepped frequency radiometer in an effort to determine its optimum operational characteristics; investigation of the classical second order analog control loop to determine its ability to reduce the estimation error in a microwave radiometer; investigation of several digital signal processing unit designs; initiation of efforts to develop required hardware and software for implementation of the digital signal processing unit; and investigation of the general characteristics and peculiarities of digital processing noiselike microwave radiometer signals.

Topics covered involve a number of closely related tasks including: the development of several control loop and dynamic noise model computer programs for simulating microwave radiometer measurements; computer modeling of an existing stepped frequency radiometer in an effort to determine its optimum operational characteristics; investigation of the classical second order analog control loop to determine its ability to reduce the estimation error in a microwave radiometer; investigation of several digital signal processing unit designs; initiation of efforts to develop required hardware and software for implementation of the digital signal processing unit; and investigation of the general characteristics and peculiarities of digital processing noiselike microwave radiometer signals.

During the past quarter we have considerable progress on the design and layout of the five-processor ring IC, although we missed the deadline for the January 1994 MOSIS 0.8 micron CMOS fabrication run. The next available run has an April 6 deadline, and we hope to have our chip on the run, or at the worst on the following one. We are trying to be as cautious as possible in our fabrication of this rather expensive chip in order to maximize our chances that only one fabrication run will be necessary. As we have mentioned previously, the chip will be drop in replacement for our one-processor chip, which was found fully functional on its first fabrication, and which was described in our previous progress report. We have also made good progress on our IBM PC boards.

The work reported in this document is concerned with the development of CAD tools, design methodologies, and architectures for the following topics of VLSI digital signal processing: high-level transformations and synthesis, discrete wavelet transform, high-speed digital subscriber loops, and finite field arithmetic for use in Reed-Solomon coders. Through this research we developed fast and efficient algorithms, ILP models, and tools that would reduce the time to explore the design space and locate an area optimal design of ASICs for DSP applications within a heterogeneous environment.

This report describes the implementation of a MIMD array computer designed and built at the Lincoln Laboratory for signal processing. Some of the software tools needed to successfully use such an array are discussed, and the software package written to allow debugging of the array from a host computer is described. The first application or the array, a 12-channel filter bank front- end for a speech recognition system, is discussed. Finally, a block diagram compiler is described. This compiler converts block diagrams, entered at a CAE workstation, into efficient assembly code for all cells in the array. Keywords include: Block diagram compiler; Digital signal processing; MIMD architecture; Multiprocessor; and Processor arrays.

This is a system description of the Naval Space Surveillance (NAVSPASUR) Sensor System Digital Signal Processing Receiver (DSPR). The NAVSPASUR system began as an advanced research project in June 1958, was commissioned as an operational Naval command in February 1961, and is operated by the Naval Space Surveillance Center (NSSC) in Dahlgren, Virginia. The DSPR is a real-time radar data acquisition and analysis system. Its function is to detect, with no prior information, all space objects whose orbits cross the continental United States and to compute their subsequent orbits. It provides vital satellite information in support of national defense mission objectives of space intelligence, satellite attack warning, satellite intercept support, and space mission support. This system description was prepared as part of a modernization program that has replaced DSPR hardware for which parts are no longer available. Volume 1 (NRL/FR/8154--93-9577) describes the DSPR system in terms of current operation and hardware and software environment. Functions of the major subsystems and the relationship between them are discussed. Volume 2 (NRL/FR/8154--93-9578) discusses the function and capabilities of software and hardware components of the subsystems that provide the digital functions of the DSPR. For each subsystem, individual software modules and hardware components used primarily by that subsystem are described.

Digital Signal Processing 

Digital Signal Processing 

Digital Signal Processing 

Digital Signal Processing 

Digital Signal Processing 

This thesis is a hardware evaluation of Rockwell International's Advanced Architecture Microprocessor (AAMP) which is a single-chlip, CMOS/SOS device. The microprocessor is evaluated by designing and testing and testing an AAMP based microcomputer system. The Electrical and Computer Engineering Department at Kansas State University has an ongoing program to evaluate microprocessors and identify those with low power consumption, easy interfacing and programming, and capability of rapid multiplications. The AAMP is a microprocessor which appears to possess these qualities. It is a high-performance, 16-bit, CMOS/SOS microprocessor and operates from a 20 MHz clock. The AAMP's instruction set is well suited for compiling from high level languages, such as Jovial and Ada, and includes, and integer, fractional, and floating-point arithmetic operations. This thesis covers the AAMP's operational characteristics, the developed microcomputer system, and the evaluation process. Special emphasis is given to the aspects of the AAMP's architecture and operational characteristics which are important in the design of a microcomputer system.

Thesis advisor(s): Therrien, C. W

Thesis advisor(s): Therrien, C. W

This is an attempt to develop a biotelemetry receiver using digital signal processing technology and techniques. The receiver developed in this work is based on recovering signals that have been encoded using either Pulse Position Modulation (PPM) or Pulse Code Modulation (PCM) technique. A prototype has been developed using state-of-the-art digital signal processing technology. A Printed Circuit Board (PCB) is being developed based on the technique and technology described here. This board is intended to be used in the UCSF Fetal Monitoring system developed at NASA. The board is capable of handling a variety of PPM and PCM signals encoding signals such as ECG, temperature, and pressure. A signal processing program has also been developed to analyze the received ECG signal to determine heart rate. This system provides a base for using digital signal processing in biotelemetry receivers and other similar applications.

This report describes the technical progress towards the development of signed processing algorithms for hybrid lidar- radar designed to improve detection performance.