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A high-level language permits a programmer to communicate easily with a computer. The machine program that results from the use of a high-level language generally executes slower and requires more of the computer resources than the same program written efficiently in machine language. An optimization pass for the language processor can reduce the execution time and the resource requirements of the resulting program. A machine independent optimization pass that accomplishes such improvements is described in this report. The algorithms that make up the optimization pass include both machine independent general algorithms and a generalization of some machine specific features. The language processor for which optimization is performed is a cross-compiler. Examples are given illustrating the results of the optimization algorithms. (Author)

The PARADIGM compiler project provides an automated means to parallelize programs, written in a serial programming model, for efficient execution on distributed-memory multicomputers. .A previous implementation of the compiler based on the PTD representation allowed symbolic array sizes, affine loop bounds and array subscripts, and variable number of processors, provided that arrays were single or multi-dimensionally block distributed. The techniques presented here extend the compiler to also accept multidimensional cyclic and block-cyclic distributions within a uniform symbolic framework. These extensions demand more sophisticated symbolic manipulation capabilities. A novel aspect of our approach is to meet this demand by interfacing PARADIGM with a powerful off-the-shelf symbolic package, Mathematica. This paper describes some of the Mathematica routines that performs various transformations, shows how they are invoked and used by the compiler to overcome the new challenges, and presents experimental results for code involving cyclic and block-cyclic arrays as evidence of the feasibility of the approach.

Jon Manning https://lca2020.linux.org.au/schedule/presentation/94/ Programmers are used to their compilers catching tiny problems in their code. When you're a writer, it's harder to catch these problems. Wouldn't it be nice if you could run an error-checker on your dialogue? This talk discusses the application of compiler optimisation and correctness checking techniques to branching narratives, which allow authors to verify the logic of their narrative independently of running it in the game. Yarn Spinner is an open source narrative design tool used in many games, including Night in the Woods (Infinite Fall / Finji) and OK KO: Let's Play Heroes (Capybara Games / Cartoon Network), that allows both writers and narrative designers to write, edit, script and manage their game's dialog using a simple scripting language that's reminiscent of Twine. While most games devise their dialog in script form, it's typically implemented using another system, such as a spreadsheet, or node-based tools. By contrast, Yarn Spinner implements a domain-specific language designed to be easy for a non-programmer to write their dialogue in, and easy for a programmer to implement gameplay-specific behaviour. Compilers for most programming languages are designed to catch common mistakes, and give warnings where appropriate. In recent years, tools for static analysis of programs - a technique where a compiler analyses the behaviour of code without running it - have allowed programmers to detect subtle bugs that a simpler compiler could not. For example, it's possible to identify a combination of branches that lead to an uninitialised variable being returned from a function. Because Yarn Spinner is a complete programming language, we are able to apply the same techniques from compiler design to assist writers. For example, a compiler is able to analyse a branching narrative tree, take into account the variables that are checked to decide what options are available, and determine that a line of dialog can never be reached. These techniques allow for more reliable testing of dialogue. Testing a branching piece of dialogue often relies on the tester repeating a number of decisions in order to set up the necessary state, which can be repetitive and tedious. However, a static analyser is able to identify what the values of certain variables _must be_ in order for a line to be accessed, which allows the tester to jump straight to the lines under test, skipping large amounts of per-test setup time. This allows someone who's trying to test out a conversation to do it in realistic conditions, skipping past the repetition while also guaranteeing that the state of the dialogue is the same as if they'd performed it manually. In this talk, I'll discuss work on Yarn Spinner that implements symbolic execution and basic block analysis, which allows writers to easily spot problems in the implementation of their narrative, saving development and testing time, and avoiding wasted production resources. Come and learn how to get started with these techniques, and how to use them in Yarn Spinner, the open source narrative design tool! linux.conf.au is a conference about the Linux operating system, and all aspects of the thriving ecosystem of Free and Open Source Software that has grown up around it. Run since 1999, in a different Australian or New Zealand city each year, by a team of local volunteers, LCA invites more than 500 people to learn from the people who shape the future of Open Source. For more information on the conference see https://linux.conf.au/ Produced by NDV: https://youtube.com/channel/UCQ7dFBzZGlBvtU2hCecsBBg?sub_confirmation=1 #linux.conf.au #linux #foss #opensource Thu Jan 16 10:45:00 2020 at Room 5

Leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. While there are several process technology and circuit-level solutions to reduce leakage in processors, the research on reducing leakage at the microarchitecture and compiler stage is still nascent. In this talk, I will present some techniques that will help reduce leakage in processors fabricated in sub nanometer technologies. ©2007 Microsoft Corporation. All rights reserved.

Maximizing parallelism level in applications can be achieved by minimizing overheads due to load imbalances and waiting time due to memory latencies. Compiler optimization is one of the most effective solutions to tackle this problem. The compiler is able to detect the data dependencies in an application and is able to analyze the specific sections of code for parallelization potential. However, all of these techniques provided with a compiler are usually applied at compile time, so they rely on static analysis, which is insufficient for achieving maximum parallelism and producing desired application scalability. One solution to address this challenge is the use of runtime methods. This strategy can be implemented by delaying certain amount of code analysis to be done at runtime. In this research, we improve the parallel application performance generated by the OP2 compiler by leveraging HPX, a C++ runtime system, to provide runtime optimizations. These optimizations include asynchronous tasking, loop interleaving, dynamic chunk sizing, and data prefetching. The results of the research were evaluated using an Airfoil application which showed a 40-50% improvement in parallel performance.

Leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. While there are several process technology and circuit-level solutions to reduce leakage in processors, the research on reducing leakage at the microarchitecture and compiler stage is still nascent. In this talk, I will present some techniques that will help reduce leakage in processors fabricated in sub nanometer technologies. ©2007 Microsoft Corporation. All rights reserved.

We have developed a compiler for the lexically-scoped dialect of LISP known as SCHEME. The compiler knows relatively little about specific data manipulation primitives such as arithmetic operators, but concentrates on general issues of environment and control. Rather than having specialized knowledge about a large variety of control and environment constructs, the compiler handles only a small basis set which reflects the semantics of lambda-calculus. All of the traditional imperative constructs, such as sequencing, assignment, looping, GOTO, as well as many standard LISP constructs such as AND, OR, and COND, are expressed as macros in terms of the applicative basis set. A small number of optimization techniques, coupled with the treatment of function calls as GOTO statements, serve to produce code as good as that produced by more traditional compilers. The macro approach enables speedy implementation of new constructs as desired without sacrificing efficiency in the generated code.

Software caching, automatic algorithm blocking, and data overlays are different names for the same problem: compiler management of data movement throughout the memory hierarchy. Modern high-performance architectures often omit hardware support for moving data between levels of the memory hierarchy: iWarp does not include a data cache, and Cray supercomputers do not have virtual memory. These systems have effectively traded a more complicated programming model for performance by replacing a hardware-controlled memory hierarchy with a simple fast memory. The simpler memories have less logic in the critical path, so the cycle time of the memories is improved. For programs which fit in the resulting memory, the extra performance is great. Unfortunately, the driving force behind supercomputing today is a class of very large scientific problems, both in terms of computation time and in terms of the amount of data used. Many of these programs do not fit in the memory of the machines available. When architects trade hardware support for data migration to gain performance, control of the memory hierarchy is left to the programmer. Either the program size must be cut down to fit into the machine, or every loop which accesses more data than will fit into memory must be restructured by hand. This thesis describes how a compiler can relieve the programmer of this burden, and automate data motion throughout the memory hierarchy without direct hardware support.

Software caching, automatic algorithm blocking, and data overlays are different names for the same problem: compiler management of data movement throughout the memory hierarchy. Modern high-performance architectures often omit hardware support for moving data between levels of the memory hierarchy: iWarp does not include a data cache, and Cray supercomputers do not have virtual memory. These systems have effectively traded a more complicated programming model for performance by replacing a hardware-controlled memory hierarchy with a simple fast memory. The simpler memories have less logic in the critical path, so the cycle time of the memories is improved. For programs which fit in the resulting memory, the extra performance is great. Unfortunately, the driving force behind supercomputing today is a class of very large scientific problems, both in terms of computation time and in terms of the amount of data used. Many of these programs do not fit in the memory of the machines available. When architects trade hardware support for data migration to gain performance, control of the memory hierarchy is left to the programmer. Either the program size must be cut down to fit into the machine, or every loop which accesses more data than will fit into memory must be restructured by hand. This thesis describes how a compiler can relieve the programmer of this burden, and automate data motion throughout the memory hierarchy without direct hardware support.

Software caching, automatic algorithm blocking, and data overlays are different names for the same problem: compiler management of data movement throughout the memory hierarchy. Modern high-performance architectures often omit hardware support for moving data between levels of the memory hierarchy: iWarp does not include a data cache, and Cray supercomputers do not have virtual memory. These systems have effectively traded a more complicated programming model for performance by replacing a hardware-controlled memory hierarchy with a simple fast memory. The simpler memories have less logic in the critical path, so the cycle time of the memories is improved. For programs which fit in the resulting memory, the extra performance is great. Unfortunately, the driving force behind supercomputing today is a class of very large scientific problems, both in terms of computation time and in terms of the amount of data used. Many of these programs do not fit in the memory of the machines available. When architects trade hardware support for data migration to gain performance, control of the memory hierarchy is left to the programmer. Either the program size must be cut down to fit into the machine, or every loop which accesses more data than will fit into memory must be restructured by hand. This thesis describes how a compiler can relieve the programmer of this burden, and automate data motion throughout the memory hierarchy without direct hardware support.

Major optimization techniques of compilers are described and grouped into three categories: machine dependent, architecture dependent, and architecture independent. Machine-dependent optimizations tend to be local and are performed upon short spans of generated code by using particular properties of an instruction set to reduce the time or space required by a program. Architecture-dependent optimizations are global and are performed while generating code. These optimizations consider the structure of a computer, but not its detailed instruction set. Architecture independent optimizations are also global but are based on analysis of the program flow graph and the dependencies among statements of source program. A conceptual review of a universal optimizer that performs architecture-independent optimizations at source-code level is also presented.

Major optimization techniques of compilers are described and grouped into three categories: machine dependent, architecture dependent, and architecture independent. Machine-dependent optimizations tend to be local and are performed upon short spans of generated code by using particular properties of an instruction set to reduce the time or space required by a program. Architecture-dependent optimizations are global and are performed while generating code. These optimizations consider the structure of a computer, but not its detailed instruction set. Architecture independent optimizations are also global but are based on analysis of the program flow graph and the dependencies among statements of source program. A conceptual review of a universal optimizer that performs architecture-independent optimizations at source-code level is also presented.

Major optimization techniques of compilers are described and grouped into three categories: machine dependent, architecture dependent, and architecture independent. Machine-dependent optimizations tend to be local and are performed upon short spans of generated code by using particular properties of an instruction set to reduce the time or space required by a program. Architecture-dependent optimizations are global and are performed while generating code. These optimizations consider the structure of a computer, but not its detailed instruction set. Architecture independent optimizations are also global but are based on analysis of the program flow graph and the dependencies among statements of source program. A conceptual review of a universal optimizer that performs architecture-independent optimizations at source-code level is also presented.