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Bell System Technical Journal, 53: 8. October 1974 pp 1477-1503. LAMP: Automatic Test Generation for Asynchronous Digital Circuits. (Chappell, S.G.)

The objective of this Phase-I study was to demonstrate the feasibility of a suite of industrial CAD tools for the design of high-performance, energy-efficient, asynchronous VLSI circuits based on the Caltech technology. Situs Logic's general strategy in the EDA-tools market is to develop and commercialize a complete suite of CAD tools for the design of asynchronous, QDI, VLSI systems including synthesis, analysis, simulation, verification, at the logical and physical levels. Situs has developed a business model for the commercialization of the CAD tools, and has designed the prototype of the tool suite based on this business model and the Caltech approach. The market for asynchronous tools will not be at first the mainstream market, but rather some 'early adopters' designing low-volume high-profit chips, for instance for defense or space applications. Inside the market segment of asynchronous VLSI tools, the competitive advantage pursued by Situs is differentiation rather than cost leadership, even though the Situs tools will be priced significantly below equivalent tools in the mainstream EDA market. The main technical activities and developments were directed towards the design of a prototype tool-site to test and demonstrate the feasibility of the approach. Although the design flow is not entirely automated yet-some steps still have to be preformed manually the results of the effort are very promising: The circuits synthesized with the prototype tool are easily competitive with the state of the art.

A new basic VLSI circuit element is presented that can be used to realize pulse mode asynchronous sequential circuits. A synthesis procedure is developed along with an unconventional state assignment procedure. Level input asynchronous sequential circuits can be realized by converting a regular flow table into a differential mode flow table, thereby allowing the new synthesis technique to be general. The new circuits tolerate 1-1 crossovers. This circuit also provides a means for state sequence detection and real time fault detection.

Scalable formal verification constitutes an important challenge for the design of asynchronous circuits. Deadlock freedom is a property that is desired but hard to verify. It is an emergent property that has to be verified monolithically. We present our approach to using ACL2 to verify necessary and sufficient conditions over asynchronous delay-insensitive primitives. These conditions are used to derive SAT/SMT instances from circuits built out of these primitives. These SAT/SMT instances help in establishing absence of deadlocks. Our verification effort consists of building an executable checker in the ACL2 logic tailored for our purpose. We prove that this checker is correct. This approach enables us to prove ACL2 theorems involving defun-sk constructs and free variables fully automatically.

Most lost of the digital design done today is synchronous that is a global synchronization signal is used to get the different parts to work in lockstep. It is simple and elegant and requires little circuit overhead. Yet as VLSI circuits increase in size and complexity. distributing global signals becomes more delicate, timing assumptions are harder to guarantee; at the system level, the global clock has to be slowed down to accommodate the slowest parts. It is interesting at this point, to consider asynchronous circuits where the time can be eliminated from the specification. A circuit is speed-independent when its correct operation is independent of delays operators circuit is delay-insensitive when its correct operation is independent of the delays in operators and wires except that the delays be finite [Sei80] [vdS85]. No global synchronization signal or knowledge about delays is used. As a subclass of asynchronous circuits delay-insensitive circuits are very interesting for formal design methods; we can reason about the correctness of such circuits independently of timing. Our research group has developed a synthesis method to compile a high level description of a circuit down to a gate level description [Mar86] [Mar90]. This compilation is largely technology- independent; only at the stage of sizing transistors for better performance do we have to look at the actual transistor network.

Physical training creates an iron cost for the body, which is a risk for young women. This study investigated a low-dose iron supplement for prevention or treatment of iron-deficiency among female RMC staff cadets and ADFA officer cadets and in so doing improve measures of fatigue, general health, physical fitness and increase participation in leisure activities. Cadets consumed either a low dose iron supplement (18 mg iron) or placebo for 13 weeks, using a double-blind, placebo-controlled randomised design. Tests at baseline, 6 wks and 13 wks determined the effects of supplement versus placebo on iron status and other measures. There was no evidence of benefit derived from the iron supplement, although emotional fatigue might have responded positively. The fatigue, health and leisure activity measures remained stable. Physical fitness improved at 6wks, but the improvement has been lost by 13 wks. Early in the semester, when cadets were most physically active, there was a mean decline in iron status as iron was mobilised from liver stores to the tissues. By the end of the semester the apparent loss from iron stores had been replenished. However more than half of the young women commenced the study with iron deficiency to some degree and this situation did not change at the 6 wk or 13 wk testing points. Self-administration of iron supplements is not recommended for the prevention or treatment of iron deficiency. The implementation of nutrition and iron-status monitoring programs are recommended.

We present a method for analyzing the time performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits-including those produced by using our synthesis method-these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.

We present a method for analyzing the time performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by the second author. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Such a metric provides a quantitative means by which to compare competing designs. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits-including those produced by using our synthesis method-these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.

Book Source: Digital Library of India Item 2015.198313 dc.contributor.author: K. Sudhir, Desai dc.date.accessioned: 2015-07-08T12:41:32Z dc.date.available: 2015-07-08T12:41:32Z dc.date.digitalpublicationdate: 2005-08-27 dc.identifier.barcode: 5990010100133 dc.identifier.origpath: /rawdataupload/upload/0100/133 dc.identifier.copyno: 1 dc.identifier.uri: http://www.new.dli.ernet.in/handle/2015/198313 dc.description.scannerno: 14 dc.description.scanningcentre: IIIT, Allahabad dc.description.main: 1 dc.description.tagged: 0 dc.description.totalpages: 120 dc.format.mimetype: application/pdf dc.language.iso: English dc.publisher: Indian Institute Of Technology Kanpur dc.rights: Out_of_copyright dc.source.library: Indian Institute Of Technology Kanpur dc.subject.classification: Technology dc.subject.classification: Engineering. Technology In General dc.subject.classification: Electrical Engineering dc.title: Design Of Asynchronous Digital Circuits

With chip size reaching one million transistors. the complexity of VLSI algorithms-i.e., algorithms implemented as a digital VLSI circuit-is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm, we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically-into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design, because the timing properties of a circuit are essential not only to its real time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason, delay. insensitive' techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: It has been proved in that the class of entirely delay-insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises to delay-insensitivity.

xi, 303 p. : 28 cm

xi, 303 p. : 28 cm

A formal hardware description language for the intended application of verifiable asynchronous communication is described. The language is developed within the logical framework of the Nqthm system of Boyer and Moore and is based on the event-driven behavioral model of VHDL, including the basic VHDL signal propagation mechanisms, the notion of simulation deltas, and the VHDL simulation cycle. A core subset of the language corresponds closely with a subset of VHDL and is adequate for the realistic gate-level modeling of both combinational and sequential circuits. Various extensions to this subset provide means for convenient expression of behavioral circuit specifications.

We define the delays of a circuit, as well as the properties of determinism, order, time invariance, constancy, symmetry and the serial connection.

We present a method for analyzing the timing performance of asynchronous circuits, in particular, those derived by program transformation from concurrent programs using the synthesis approach developed by Martin. The analysis method produces a performance metric (related to the time needed to perform an operation) in terms of the primitive gate delays of the circuit. Because the gate delays are functions of transistor sizes, the performance metric can be optimized with respect to these sizes. For a large class of asynchronous circuits - including those produced by Martin synthesis - these techniques produce the global optimum of the performance metric. A CAD tool has been implemented to perform this optimization.

We have described three algorithms for distributed mutual exclusion on a ring. All algorithms use a token to select a candidate. We have already implemented the most efficient of these algorithms as an asynchronous VLSI circuit. We are now going to implement the simplest one. An arbitrary number ( 1) of cyclic automata, called masters, make independent requests for exclusive access to a shared resource. The circuit should handle the requests from the masters in such a way that any request is eventually granted, and there is at most one master using the shared resource at any time. The masters are independent of each other: They do not communicate with each other, and the activity of a master not using the resource should not influence the activity of other masters. A master, M, communicates with its private server, m. When M wants to use the shared resource (M is said to be a candidate), it issues a request to m. When the request is accepted, M uses that resource (for a finite period of time), and then informs m that the resource is free again. The servers are connected in a ring. At any time, exactly one (arbitrary) server holds a privilege, or token. The token circulates continuously around the ring of servers, and only the server that holds the token may grant the resource to its master, which guarantees mutual exclusion on the access to the resource.

We have described three algorithms for distributed mutual exclusion on a ring. All algorithms use a token to select a candidate. We have already implemented the most efficient of these algorithms as an asynchronous VLSI circuit. We are now going to implement the simplest one. An arbitrary number ( 1) of cyclic automata, called masters, make independent requests for exclusive access to a shared resource. The circuit should handle the requests from the masters in such a way that any request is eventually granted, and there is at most one master using the shared resource at any time. The masters are independent of each other: They do not communicate with each other, and the activity of a master not using the resource should not influence the activity of other masters. A master, M, communicates with its private server, m. When M wants to use the shared resource (M is said to be a candidate), it issues a request to m. When the request is accepted, M uses that resource (for a finite period of time), and then informs m that the resource is free again. The servers are connected in a ring. At any time, exactly one (arbitrary) server holds a privilege, or token. The token circulates continuously around the ring of servers, and only the server that holds the token may grant the resource to its master, which guarantees mutual exclusion on the access to the resource.

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Seminal Technical report 66: Algebra and Proofs for asynchronous digital circuits. The 2-input, 1-output C-Gate , is derived and described.  The C-Gate output will tend toward the value of the two inputs whenever they agree. Otherwise the output will remain at its previous value. The Algebra is shown to be usefully extendable to more complex circuits.  The copies at:  http://archive.org/details/theoryofasynchro66mull  are very helpful, but the OCR is machine output.  Based on the scanned images from the document above, a PDF was prepared that was subsequently OCR-ed, and edited to match the text and layout by: Gary Delp and uploaded to the Internet Archive: 11 May 2020 The pages, as digitized, included hand drawn marks; these have been converted to code points in the table below:  Symbol     L A T E X       Code Point  ∪ \cup 8746  ∩ \cap 8745  = \Equal 0061  ≈ \approx 8776  ≠ \ne 8800  ≥ \geq 8805  ≤ \leq 8804

A formal hardware description language for the intended application of verifiable asynchronous communication is described. The language is developed within the logical framework of the Nqthm system of Boyer and Moore and is based on the event-driven behavioral model of VHDL, including the basic VHDL signal propagation mechanisms, the notion of simulation deltas, and the VHDL simulation cycle. A core subset of the language corresponds closely with a subset of VHDL and is adequate for the realistic gate-level modeling of both combinational and sequential circuits. Various extensions to this subset provide means for convenient expression of behavioral circuit specifications.

A systematic approach for evaluating and optimizing the performance of asynchronous VLSI circuits is presented. Index-priority simulation is introduced to efficiently find minimal cycles in the state graph of a given circuit. These minimal cycles are used to determine the causality relationships between all signal transitions in the circuit. once these relationships are known, the circuit is then modeled as an extended event-rule system, which can be used to describe many circuits, including ones that are inherently disjunctive. An accurate indication of the performance of the circuit is obtained by analytically computing the period of the corresponding extended event-rule system.

Algorithm for synthesis of asynchronous sequential circuits

The editing and typeset version of https://archive.org/details/theoryofasynchro66mull paper text, but typeset with various fonts and the mathematics moved to text form.  Includes indications for the original pagination.  Figures are redrawn and the handwritten symbols are now typeset. (David E. Muller wrote this in 1955.  He did a great job!)

The editing and typeset version of https://archive.org/details/theoryofasynchro66mull paper text, but typeset with various fonts and the mathematics moved to text form.  Includes indications for the original pagination.  Figures are redrawn and the handwritten symbols are now typeset. (David E. Muller wrote this in 1955.  He did a great job!)

This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ``bridge'' between static logic analysis and detailed simulation.

We present the bounded delays, the absolute inertia and the relative inertia.

We present the bounded delays, the absolute inertia and the relative inertia.

Book Source: Digital Library of India Item 2015.191750 dc.contributor.author: Ajay Kumar Garg dc.date.accessioned: 2015-07-08T01:09:43Z dc.date.available: 2015-07-08T01:09:43Z dc.date.digitalpublicationdate: 2005-08-27 dc.identifier.barcode: 1990010086587 dc.identifier.origpath: /rawdataupload/upload/0086/587 dc.identifier.copyno: 1 dc.identifier.uri: http://www.new.dli.ernet.in/handle/2015/191750 dc.description.scannerno: 14 dc.description.scanningcentre: IIIT, Allahabad dc.description.main: 1 dc.description.tagged: 0 dc.description.totalpages: 74 dc.format.mimetype: application/pdf dc.language.iso: English dc.publisher: Indian Institute Of Technology Kanpur dc.rights: Out_of_copyright dc.source.library: Indian Institute Of Technology Kanpur dc.subject.classification: Technology dc.subject.classification: Engineering. Technology In General dc.subject.classification: Mechanical Engineering In General. Nuclear Technology. Electrical Engineering. Machinery dc.title: Design And Synthesis Of Asynchronous Digital Circuits

This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.

This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.

This paper introduces an improved method for designing the class of CMOS VLSI asynchronous sequential circuits introduced in the paper by Sterling R. Whitaker and Gary K. Maki, 'Self Arbitrated VLSI Asynchronous Circuits.' Of main interest here is the simple design by inspection rules that arise from these circuits. This paper presents a variation on these circuits which reduces the number of transistors required.

"December 6, 1955"

"January 6, 1960."

"January 6, 1960."