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The implementation of a low power logic based asynchronous circuit with the help of power gated logic. In asynchronous power gated logic (APL) circuit, each pipeline stage was incorporated with efficient charge recovery logic (ECRL) gate; handshake controller and partial charge reuse (PCR) mechanism. The main objective was, to provide a new lower power solutions using power gating (PG) for very large scale integration (VLSI) designers. ECRL have the simplest structure and high energy efficiency which was used to implement the functional blocks of APL circuit. PG adopts two approaches, fine grain and coarse grain approach. The circuit based asynchronous with fine grain approach is called asynchronous fine grain power gated logic (AFPL) circuit and coarse grain approach is said to be asynchronous coarse grain power gated logic (ACPL) circuit. In the PCR mechanism, part of the charge on the output node of an ECRL gate was reused to charge the output node of another ECRL gate. This help to reducing the energy dissipation. Therefore, leakage power reduction should begin with power gated logic and PCR mechanism. To mitigate the area overhead of the AFPL circuit, coarse grain power gating technique have been developed.

The implementation of a low power logic based asynchronous circuit with the help of power gated logic. In asynchronous power gated logic (APL) circuit, each pipeline stage was incorporated with efficient charge recovery logic (ECRL) gate; handshake controller and partial charge reuse (PCR) mechanism. The main objective was, to provide a new lower power solutions using power gating (PG) for very large scale integration (VLSI) designers. ECRL have the simplest structure and high energy efficiency which was used to implement the functional blocks of APL circuit. PG adopts two approaches, fine grain and coarse grain approach. The circuit based asynchronous with fine grain approach is called asynchronous fine grain power gated logic (AFPL) circuit and coarse grain approach is said to be asynchronous coarse grain power gated logic (ACPL) circuit. In the PCR mechanism, part of the charge on the output node of an ECRL gate was reused to charge the output node of another ECRL gate. This help to reducing the energy dissipation. Therefore, leakage power reduction should begin with power gated logic and PCR mechanism. To mitigate the area overhead of the AFPL circuit, coarse grain power gating technique have been developed.

Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.

The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.

1Stories of Enchantment

By Jane Pentzer Myers

Jane Pentzer Myers's only book was dedicated to Kate Winifred: 'Just between the 'Land o' dreams' and broad daylight is a beautiful world, where good wishes come true: where the poor and lonely are rich in castles and friends: and where sorrowful folk are happy.' These twelve charming tales transport us to that wonderful land of dreams and delight and enchant children of all ages. ( Lynne Thompson)