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Tri 2 2016/2017

Tri 2 2015/2016

Tri 2 2015/2016

Tri 2 2015/2016

This report describes the requirements for an advanced automated weld system and the associated computer architecture, and defines the overall system specification from a broad perspective. According to the requirements of welding procedures as they relate to an integrated multiaxis motion control and sensor architecture, the computer system requirements are developed based on a proven multiple-processor architecture with an expandable, distributed-memory, single global bus architecture, containing individual processors which are assigned to specific tasks that support sensor or control processes. The specified architecture is sufficiently flexible to integrate previously developed equipment, be upgradable and allow on-site modifications.

Advanced Computer Architecture from NPTEL IIT Guwahati

Advanced Computer Architecture from NPTEL IIT Guwahati

This exploratory development program was originally aimed at developing a computer with features to specifically support the JOVIAL (J73) programming language with considerations to Ada. Later, the program was redirected to modify the instruction set architecture (ISA) to more fully support Ada and increase performance. The new ISA supports most of the standard functions found in most ISA, but gives additional supports in: the Ada package concept, processing arrays nd records, unconstrained arrays, dynamic storage allocation, detecting dangling references, detecting undefined variables, Ada-like exception handling, case instructions, for-loop instructions, Ada-like parameter passing, Ada-like tasking instructions and IEEE-standard floating point data types. Keywords: High level language Ada machine, Semantic gap reduction; Language-directed architecture; Non-Von Neumann architecture; Object oriented architecture; Capability based addressing.

Tri 1 2015/2016

Tri 1 2015/2016

Tri 2 2017/2018

Trimester 2 2022/2023

Tri 2 2018/2019

TRI 2, 2019/2020

The redesigned Advanced Unmanned Search System (AUSS) surface control van has been based on the IBM PC/AT, a well-known, commercially available computer. Its installed market base has made hardware add-on components widely available. The market dominance of Microsoft's DOS has standardized the operating system software. The surface control van computers' functions have been split among several machines to provide for some modularity of the software design and accommodate possible increased processing demands. Operating system software and hardware architecture for these six 7552-based PCs are detailed. The author recommends redefining the AUSS surface computer to be an X Window Platform, an architecture that can provide a virtual display environment. The virtual display environment would protect the software development investment from obsolescence due to hardware technology advances, reduce sparing requirements, and simplify the control van wiring. Appendices describe board jumpers, switch settings, and boot configurations for the six 7552-based PCs.... IBM 7552 PC, X Window system, MULTIBUS I and II.

The redesigned Advanced Unmanned Search System (AUSS) surface control van has been based on the IBM PC/AT, a well-known, commercially available computer. Its installed market base has made hardware add-on components widely available. The market dominance of Microsoft's DOS has standardized the operating system software. The surface control van computers' functions have been split among several machines to provide for some modularity of the software design and accommodate possible increased processing demands. Operating system software and hardware architecture for these six 7552-based PCs are detailed. The author recommends redefining the AUSS surface computer to be an X Window Platform, an architecture that can provide a virtual display environment. The virtual display environment would protect the software development investment from obsolescence due to hardware technology advances, reduce sparing requirements, and simplify the control van wiring. Appendices describe board jumpers, switch settings, and boot configurations for the six 7552-based PCs.... IBM 7552 PC, X Window system, MULTIBUS I and II.

Improvements and advances in the development of computer architecture now provide innovative technology for the recasting of traditional sequential solutions into high-performance, low-cost, parallel system to increase system performance. Research conducted in development of specialized computer architecture for the algorithmic execution of an avionics system, guidance and control problem in real time is described. A comprehensive treatment of both the hardware and software structures of a customized computer which performs real-time computation of guidance commands with updated estimates of target motion and time-to-go is presented. An optimal, real-time allocation algorithm was developed which maps the algorithmic tasks onto the processing elements. This allocation is based on the critical path analysis. The final stage is the design and development of the hardware structures suitable for the efficient execution of the allocated task graph. The processing element is designed for rapid execution of the allocated tasks. Fault tolerance is a key feature of the overall architecture. Parallel numerical integration techniques, tasks definitions, and allocation algorithms are discussed. The parallel implementation is analytically verified and the experimental results are presented. The design of the data-driven computer architecture, customized for the execution of the particular algorithm, is discussed.

The objective of the study was to define an advanced guidance computer architecture that will permit the effective use of high-order programming languages in the definition and implementation of advanced ballistic missile missions. Part 2 of the Final Report entitled 'Guidance Computer Architecture Study', contains the selected architecture together with the SPL language and compiler considerations involved in the design, and the programming tradeoff studies. The study placed emphasis on the ability of the architecture to efficiently execute compiler generated code. A selected set of guidance and targeting equations was used as a vehicle for conducting tradeoff studies. SPL compiler generated code forms were studied for interfacing with computer functions. The size efficiency of the object code compared to that of assembly programming for traditional single address fixed point airborne computer architectures was the major design consideration. The resulting architecture is effective in satisfying other functional guidance computer system requirements (i.e. execution time and memory size) while significantly improving the size efficiency of generated object code.

The objective of the study was to define an advanced guidance computer architecture that will permit the effective use of high-order programming languages in the definition and implementation of advanced ballistic missile missions. Part 2 of the Final Report entitled 'Guidance Computer Architecture Study', contains the selected architecture together with the SPL language and compiler considerations involved in the design, and the programming tradeoff studies. The study placed emphasis on the ability of the architecture to efficiently execute compiler generated code. A selected set of guidance and targeting equations was used as a vehicle for conducting tradeoff studies. SPL compiler generated code forms were studied for interfacing with computer functions. The size efficiency of the object code compared to that of assembly programming for traditional single address fixed point airborne computer architectures was the major design consideration. The resulting architecture is effective in satisfying other functional guidance computer system requirements (i.e. execution time and memory size) while significantly improving the size efficiency of generated object code.

The objective of the study was to define an advanced guidance computer architecture that will permit the effective use of high-order programming languages in the definition and implementation of advanced ballistic missile missions. Part 2 of the Final Report entitled 'Guidance Computer Architecture Study', contains the selected architecture together with the SPL language and compiler considerations involved in the design, and the programming tradeoff studies. The study placed emphasis on the ability of the architecture to efficiently execute compiler generated code. A selected set of guidance and targeting equations was used as a vehicle for conducting tradeoff studies. SPL compiler generated code forms were studied for interfacing with computer functions. The size efficiency of the object code compared to that of assembly programming for traditional single address fixed point airborne computer architectures was the major design consideration. The resulting architecture is effective in satisfying other functional guidance computer system requirements (i.e. execution time and memory size) while significantly improving the size efficiency of generated object code.

This exploratory development program was originally aimed at developing a computer with features to specifically support the JOVIAL (J73) programming language with considerations to Ada. Later, the program was redirected to modify the instruction set architecture (ISA) to more fully support Ada and increase performance. The new ISA supports most of the standard functions found in most ISA, but gives additional supports in: the Ada package concept, processing arrays and records, unconstrained arrays, dynamic storage allocation, detecting dangling reference, detecting undefined variables, Ada-like exception handling, case instructions, for-loop instructions, Ada-like parameter passing, Ada-like tasking instructions and IEEE-standard floating point data types. Keywords: High level language Ada machine, Semantic gap reduction; Language-directed architecture; Non-Von Neumann architecture; Object oriented architecture; Capability based addressing.

This exploratory development program was originally aimed at developing a computer with features to specifically support the JOVIAL (J73) programming language with considerations to Ada. Later, the program was redirected to modify the instruction set architecture (ISA) to more fully support Ada and increase performance. The new ISA supports most of the standard functions found in most ISA, but gives additional supports in: the Ada package concept, processing arrays and records, unconstrained arrays, dynamic storage allocation, detecting dangling reference, detecting undefined variables, Ada-like exception handling, case instructions, for-loop instructions, Ada-like parameter passing, Ada-like tasking instructions and IEEE-standard floating point data types. Keywords: High level language Ada machine, Semantic gap reduction; Language-directed architecture; Non-Von Neumann architecture; Object oriented architecture; Capability based addressing.