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Cyclic Spectrum Analysis exploits the cyclostationary properties of signals and systems. Military use of this technology is focused on its use in a near real time analytical environment. Such a system requires high speed arithmetic processing in calculating large Fourier transforms quickly. This thesis reviews a previous implementation and then presents a new design using Verilog hardware description language and the Epoch silicon compiler. Using these modern computer aided design tools, the ASIC design was simulated and layout completed using a one micron, two-metal process rule set. The final layout consists of 434,138 transistors on a 11,190 x 15,642 micron die. Simulations indicated that the chip would be capable of operating at a 25 Mhz clock rate while dissipating .8 watts of power. Embedded timing analysis tools displayed all critical timing paths which allowed the identification of specific design improvements. If implemented, these changes could double the clock rate of the processor.

Cyclic Spectrum Analysis exploits the cyclostationary properties of signals and systems. Military use of this technology is focused on its use in a near real time analytical environment. Such a system requires high speed arithmetic processing in calculating large Fourier transforms quickly. This thesis reviews a previous implementation and then presents a new design using Verilog hardware description language and the Epoch silicon compiler. Using these modern computer aided design tools, the ASIC design was simulated and layout completed using a one micron, two-metal process rule set. The final layout consists of 434,138 transistors on a 11,190 x 15,642 micron die. Simulations indicated that the chip would be capable of operating at a 25 Mhz clock rate while dissipating .8 watts of power. Embedded timing analysis tools displayed all critical timing paths which allowed the identification of specific design improvements. If implemented, these changes could double the clock rate of the processor.