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The cover of “Designing asynchronous circuits using NULL convention logic (NCL)” - Open Library.

"Designing asynchronous circuits using NULL convention logic (NCL)" was published by Morgan & Claypool Publishers in 2009 - San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) and the language of the book is English.


“Designing asynchronous circuits using NULL convention logic (NCL)” Metadata:

  • Title: ➤  Designing asynchronous circuits using NULL convention logic (NCL)
  • Author:
  • Language: English
  • Publisher: Morgan & Claypool Publishers
  • Publish Date:
  • Publish Location: ➤  San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)

“Designing asynchronous circuits using NULL convention logic (NCL)” Subjects and Themes:

Edition Specifications:

  • Format: [electronic resource] /

Edition Identifiers:

AI-generated Review of “Designing asynchronous circuits using NULL convention logic (NCL)”:


"Designing asynchronous circuits using NULL convention logic (NCL)" Table Of Contents:

  • 1- Introduction to asynchronous logic
  • 2- Overview of NULL convention logic (NCL)
  • 3- NCL system framework and fundamental components
  • 4- Transistor-level NCL gate design
  • 5- Combinational NCL circuit design
  • 6- Input-completeness and observability
  • 7- Dual-rail NCL design
  • 8- Quad-rail NCL design
  • 9- Sequential NCL circuit design
  • 10- NCL implementation of Mealy and Moore machines
  • 11- NCL implementation of algorithmic state machines
  • 12- NCL throughput optimization
  • 13- Pipelining
  • 14- Embedded registration
  • 15- Early completion
  • 16- NULL cycle reduction
  • 17- Low-power NCL design
  • 18- Wavefront steering
  • 19- Multi-threshold CMOS (MTCMOS) for NCL (MTNCL)
  • 20- MTCMOS for synchronous circuits
  • 21- Implementing MTCMOS in NCL circuits
  • 22- Comprehensive NCL design example.

"Designing asynchronous circuits using NULL convention logic (NCL)" Description:

The Open Library:

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power.

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