Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization - Info and Reading Options
By Hairong Gao
"Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization" was published in 1997 - xx , it has 42 pages and the language of the book is English.
“Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization” Metadata:
- Title: ➤ Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization
- Author: Hairong Gao
- Language: English
- Number of Pages: 42
- Publish Date: 1997
- Publish Location: xx
“Design of high-speed summing circuitry and comparator for adaptive parallel multi-level decision feedback equalization” Subjects and Themes:
- Subjects: ➤ Feedback control systems - Parallel processing (Electronic computers) - Analog-to-digital converters - Computer arithmetic - Design and construction
Edition Specifications:
- Pagination: 42 leaves, bound :
Edition Identifiers:
- The Open Library ID: OL18111855M - OL11591035W
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