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The cover of “Design of CMOS RF integrated circuits and systems” - Open Library.

"Design of CMOS RF integrated circuits and systems" was published by World Scientific in 2010 - Singapore, it has 341 pages and the language of the book is English.


“Design of CMOS RF integrated circuits and systems” Metadata:

  • Title: ➤  Design of CMOS RF integrated circuits and systems
  • Author:
  • Language: English
  • Number of Pages: 341
  • Publisher: World Scientific
  • Publish Date:
  • Publish Location: Singapore

“Design of CMOS RF integrated circuits and systems” Subjects and Themes:

Edition Specifications:

  • Pagination: xv, 341 p. :

Edition Identifiers:

AI-generated Review of “Design of CMOS RF integrated circuits and systems”:


"Design of CMOS RF integrated circuits and systems" Table Of Contents:

  • 1- Chapter 1. RF CMOS Systems on Chips
  • 2- 1.1. Modern RF Mobile Technologies
  • 3- 1.2. The RF Transceiver System
  • 4- 1.3. Modulation and Demodulation Techniques
  • 5- 1.4. Multiple Access Techniques
  • 6- 1.5. Receiver Sensitivity and Linearity
  • 7- 1.6. On-chip Power Amplifier
  • 8- 1.7. The Cellular Phone Concept
  • 9- 1.8. The CMOS RF Technology
  • 10- References
  • 11- Chapter 2. RF CMOS Devices and Process Design Kits
  • 12- 2.1. Introduction
  • 13- 2.2. RF Transistors
  • 14- 2.2.1. BSIM3v3 Model
  • 15- 2.2.2. BSIM4 Model
  • 16- 2.2.3. Figure of Merit
  • 17- 2.2.3.1. fT definition and extraction
  • 18- 2.2.3.2. fMAX definition and extraction
  • 19- 2.2.4. RF Parasitics in MOSFETs
  • 20- 2.2.5. Scalable RF CMOS Transistor Modeling
  • 21- 2.2.5.1. RF MOSFET model
  • 22- 2.2.5.2. Gate resistance modeling
  • 23- 2.2.5.3. Source and drain resistance modeling
  • 24- 2.2.5.4. Gate to substrate capacitance and resistance modeling
  • 25- 2.2.5.5. Gate to source and gate to drain capacitance modeling
  • 26- 2.2.5.6. Drain to source capacitance modeling
  • 27- 2.2.5.7. Substrate resistance modeling
  • 28- 2.3. On-chip Inductors
  • 29- 2.3.1. Spiral Inductors on Silicon
  • 30- 2.3.1.1. Figure of merits
  • 31- 2.3.2. Advantages of Silicon-based Spiral Inductors
  • 32- 2.3.3. Identifying Loss Mechanisms in Silicon-based Spiral Inductors
  • 33- 2.3.3.1. Metallization resistive loss
  • 34- 2.3.3.2. Substrate capacitive and resistive loss
  • 35- 2.3.3.3. Substrate eddy current
  • 36- 2.3.4. Q-Factor Enhancement Techniques
  • 37- 2.3.4.1. Q-factor enhancement using processing technologies
  • 38- 2.3.4.2. Q-factor enhancement using active inductors
  • 39- 2.3.4.3. Q-factor enhancement using coupled spiral coils
  • 40- 2.3.4.4. Q-factor enhancement using layout optimization
  • 41- 2.3.4.5. Q-factor enhancement using inductor device model
  • 42- 2.3.4.6. Figure of merits for differential spiral inductors
  • 43- 2.4. Baluns/Transformers
  • 44- 2.4.1. The Ideal Transformer
  • 45- 2.4.2. Transformer Types
  • 46- 2.4.3. Inductance, Capacitance, and Resistance
  • 47- 2.4.4. Coupling Coefficient k, Turn Ratio n, and Quality Factor Q
  • 48- 2.4.5. Patterned Ground Shield
  • 49- 2.4.6. Designing the Transformer
  • 50- 2.5. RF Interconnects
  • 51- 2.5.1. Transmission Line Concept
  • 52- 2.5.1.1. Transmission line constants
  • 53- 2.5.1.2. Transmission line impedances
  • 54- 2.5.1.3. Reflection and voltage standing wave ratio
  • 55- 2.5.1.4. Frequency-dependent charge distribution
  • 56- 2.5.1.5. Effects of dielectric on interconnects
  • 57- 2.5.2. Existing Methodologies to Tackle Post Layout Parasitics
  • 58- 2.5.3. Proposed Figure of Merit for RF Interconnects
  • 59- 2.6. Varactors
  • 60- 2.6.1. Functions of Varactors
  • 61- 2.6.2. Varactor Design
  • 62- 2.7. RF Capacitors
  • 63- 2.7.1. Capacitance
  • 64- 2.7.2. Geometry
  • 65- 2.7.3. Quality Factor and Series Resistance
  • 66- 2.7.4. Capacitance Modeling
  • 67- 2.7.5. Impedances
  • 68- 2.7.6. Design Considerations
  • 69- 2.8. Process Design Kits
  • 70- 2.8.1. Benefits
  • 71- 2.8.2. Advanced Device Modeling and Front-end Design
  • 72- 2.8.3. Back-end Design and Accelerated Layout
  • 73- 2.8.4. Physical Verification and Silicon Analysis
  • 74- 2.8.5. Future of Process Design Kits
  • 75- 2.9. Summary
  • 76- References
  • 77- Chapter 3. RF CMOS Low Noise Amplifiers
  • 78- 3.1. Basic Concepts of LNAs
  • 79- 3.1.1. Operating Frequency
  • 80- 3.1.2. Sensitivity
  • 81- 3.1.3. Noise Figure and Voltage Gain
  • 82- 3.1.4. 1 -dB Compression Point
  • 83- 3.1.5. The 3rd Order Intercept Point
  • 84- 3.1.6. S-Parameters
  • 85- 3.2. Input Architecture of LNAs
  • 86- 3.2.1. Common Source Stage with Resistive Termination
  • 87- 3.2.2. Common Gate Stage
  • 88- 3.2.3. Common Source Stage with Shunt Feedback
  • 89- 3.2.4. Common Source Stage with Source Inductive Degeneration
  • 90- 3.3. Input Matching Analysis
  • 91- 3.4. Design of a Single-band LNA (LNA1)
  • 92- 3.4.1. Noise Figure Optimization
  • 93- 3.4.2. Design Methodology
  • 94- 3.4.3. Measurement Results
  • 95- 3.5. Summary
  • 96- References
  • 97- Chapter 4. RF Mixers
  • 98- 4.1. Introduction
  • 99- 4.2. Common Configurations of Active Mixers
  • 100- 4.3. Active Mixer with Current Booster
  • 101- 4.4. Passive Mixers
  • 102- 4.5. Port Isolation and DC Offset in Direct Conversion Mixers
  • 103- 4.6. Image Reject Mixers for Low IF Architectures
  • 104- References
  • 105- Chapter 5. RF CMOS Oscillators
  • 106- 5.1. Introduction
  • 107- 5.1.1. Ring Oscillator
  • 108- 5.1.2. LC Oscillator
  • 109- 5.2. Various LC VCO Topologies
  • 110- 5.2.1. Colpitts and HartleyLC VCOs
  • 111- 5.2.2. Differential LC VCOs
  • 112- 5.2.2.1. Complementary LC VCOs
  • 113- 5.2.2.2. Tail current source of LC VCOs
  • 114- 5.3. LC VCO Design Methodology
  • 115- 5.3.1. Topology
  • 116- 5.3.1.1. Operation theory
  • 117- 5.3.1.2. Equivalent circuit of cross-coupled LC tank VCO
  • 118- 5.3.2. Associated Noise Sources of Complementary LC Tank VCO
  • 119- 5.3.2.1. Noise sources of the LC tank
  • 120- 5.3.2.2. Upconversion of 1/f noise in the tail transistor
  • 121- 5.3.3. Noise Sources in Active Devices
  • 122- 5.3.3.1. High frequency noise
  • 123- 5.3.3.2. Noise sources in cross-coupled transistors
  • 124- 5.3.3.3. Optimization of channel length Lch
  • 125- 5.3.4. Linear Time Variant (LTV) Phase Noise Analysis
  • 126- 5.3.4.1. Definition of Impulse Sensitivity Function (ISF)-Γ(ω0t)
  • 127- 5.3.4.2. Parameterized phase impulse response hφ (t, τ) using ISF
  • 128- 5.3.4.3. Phase noise calculation
  • 129- 5.3.4.4. Steps to achieve minimal phase noise
  • 130- 5.3.5. A 2GHz Cross-Coupled LC Tank VCO
  • 131- 5.3.5.1. 2GHz cross-coupled LC tank VCO
  • 132- 5.3.5.2. Verifications and discussions
  • 133- 5.3.5.3. Experimental results
  • 134- 5.3.6. A 9.3 ̃10.4GHz Cross-Coupled Complementary Oscillator
  • 135- 5.3.6.1. Phase noise estimation for 10GHzLC tank VCO
  • 136- 5.3.6.2. Experimental results
  • 137- 5.4. Summary
  • 138- References
  • 139- Chapter 6. RF CMOS Phase-Locked Loops
  • 140- 6.1. Fundamental Principles of a Phase-Locked Loop (PLL)
  • 141- 6.2. Transient Characteristics - Tracking
  • 142- 6.3. Loop Bandwidth - Second Order PLL
  • 143- 6.4. Acquisition
  • 144- 6.5. Phase Detector and Loop Filter
  • 145- 6.5.1. Phase Detector
  • 146- 6.5.1.1. Multiplier
  • 147- 6.5.1.2. EXOR gate
  • 148- 6.5.1.3. Flip-flop phase detector
  • 149- 6.5.1.4. Phase frequency detector
  • 150- 6.5.2. Loop Filter
  • 151- 6.6. Charge Pump PLL Filter
  • 152- 6.7. Noise Characteristics of PLL Building Blocks
  • 153- 6.7.1. Phase Noise of VCO
  • 154- 6.7.2. Phase Noise of Reference Input Signal
  • 155- 6.7.3. Phase Noise of Frequency Divider
  • 156- 6.7.4. Phase Noise of Loop Filter
  • 157- 6.7.5. Optimum Loop Bandwidth
  • 158- 6.8. Summary
  • 159- References
  • 160- Chapter 7. RF CMOS Prescalers
  • 161- 7.1. Prescaler
  • 162- 7.1.1. Dual-Modulus Prescaler
  • 163- 7.1.2. Dual-Modulus Prescaler with Pulse Swallow Counter
  • 164- 7.1.3. Integer-N Architecture through Dual-Modulus Prescaler with Pulse Swallow Counter
  • 165- 7.2. DFFs for Prescaler
  • 166- 7.2.1. MCML
  • 167- 7.2.2. CMOS Dynamic Circuit
  • 168- 7.3. Design and Optimization of CMOS Dynamic Circuit (CDC) Based Prescaler
  • 169- 7.3.1. E-TSPC Based Divide-by-2 Unit
  • 170- 7.3.2. E-TSPC Based Divide-by-2/3 Unit
  • 171- 7.3.3. Design Example
  • 172- 7.3.4. Simulation and Silicon Verifications
  • 173- 7.4. Summary
  • 174- References.

"Design of CMOS RF integrated circuits and systems" Description:

The Open Library:

"This book provides the most comprehensive and in-depth coverage of the latest circuit design developments in RF CMOS technology. It is a practical and cutting-edge guide, packed with proven circuit techniques and innovative design methodologies for solving challenging problems associated with RF integrated circuits and systems. This invaluable resource features a collection of the finest design practices that may soon drive the system-on-chip revolution. Using this book's state-of-the-art design techniques, one can apply existing technologies in novel ways and to create new circuit designs for the future."--BOOK JACKET.

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