A unified approach for timing verification and delay fault testing - Info and Reading Options
By Mukund Sivaraman
"A unified approach for timing verification and delay fault testing" was published by Kluwer Academic in 1998 - Boston, it has 155 pages and the language of the book is English.
“A unified approach for timing verification and delay fault testing” Metadata:
- Title: ➤ A unified approach for timing verification and delay fault testing
- Author: Mukund Sivaraman
- Language: English
- Number of Pages: 155
- Publisher: Kluwer Academic
- Publish Date: 1998
- Publish Location: Boston
“A unified approach for timing verification and delay fault testing” Subjects and Themes:
- Subjects: ➤ Digital integrated circuits - Data processing - Delay faults (Semiconductors) - Verification - Testing - Integrated circuits - Design and construction - Electric fault location
Edition Specifications:
- Pagination: xv, 155 p. :
Edition Identifiers:
- The Open Library ID: OL694728M - OL2732328W
- Online Computer Library Center (OCLC) ID: 37713039
- Library of Congress Control Number (LCCN): 97042061
- ISBN-13: 9780792380795
- ISBN-10: 0792380797
- All ISBNs: 0792380797 - 9780792380795
AI-generated Review of “A unified approach for timing verification and delay fault testing”:
"A unified approach for timing verification and delay fault testing" Description:
The Open Library:
A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously reported floating mode timing analyzers. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in USLI circuits. The book should also be of interest to digital designers and others interested in knowing the state-of-the-art in timing verification and delay fault testing.
Read “A unified approach for timing verification and delay fault testing”:
Read “A unified approach for timing verification and delay fault testing” by choosing from the options below.
Search for “A unified approach for timing verification and delay fault testing” downloads:
Visit our Downloads Search page to see if downloads are available.
Find “A unified approach for timing verification and delay fault testing” in Libraries Near You:
Read or borrow “A unified approach for timing verification and delay fault testing” from your local library.
- The WorldCat Libraries Catalog: Find a copy of “A unified approach for timing verification and delay fault testing” at a library near you.
Buy “A unified approach for timing verification and delay fault testing” online:
Shop for “A unified approach for timing verification and delay fault testing” on popular online marketplaces.
- Ebay: New and used books.